Ordinary CMOS (complementary metal-oxide semiconductor) image sensors include a pixel array and a reading unit. A photodiode and an amplifier circuit are included for each pixel of the pixel array. The voltage generated by the photodiode is amplified by the amplifier circuit and output on a column signal line. The reading unit reads each pixel twice for noise cancelation processing. This is called correlated double sampling (CDS). The image signals at the dark level (N) and signal level (NS) are each read. The new pixel signal (S) is obtained from the difference of these signals (N-NS). Analog-digital conversion (ADC) is performed for pixel signal (S) following CDS for further image processing.
Each pixel is read using a technique combining a parallel system and a sequential system. Each row of the pixel array is selected in succession. Pixel signals are read in parallel from multiple columns in the selected row. The degree of parallelism changes according to the extent of read processing performed in each column. Table 1 shows the details of read processing performed in each column and the degree of parallelism.
TABLE 1N/NSSignalADParallelismmemoryCDSamplificationconversionLow◯———Moderate◯◯◯—High◯◯◯◯
Improved parallelism improves performance while keeping power consumption low. This is because integration of pixels at the column level is strongly promoted when image sensor resolution is increased. In recent years, CMOS image sensors include an amplifying circuit for each column.
FIG. 26 shows an example of an ordinary switched capacitor amplifier that performs amplification and CDS of pixel signals in an image sensor of the prior art.
The amplifier shown in FIG. 26 has capacitors Ca and Cb, an operational amplifier 101 and a switch circuit 102. One terminal of capacitor Ca is connected to a column signal line of the image sensor and the other terminal is connected to the negative input terminal of operational amplifier 101. Capacitor Cb and switch circuit 102 are connected in parallel between the negative input terminal and the output terminal Vout of operational amplifier 101. Reference voltage GND is input to the positive input terminal of operational amplifier 101.
When dark level voltage Vn is output from the image sensor, switch circuit 102 is ON. The negative input terminal of operational amplifier 101 is held approximately at reference voltage GND so voltage Vn is supplied to capacitor Ca. The charge in capacitor Cb is cleared by switch circuit 102 being ON.
When signal level voltage Vns is output from the image sensor, switch circuit 102 goes OFF. The negative input terminal of operational amplifier 101 is held approximately at reference voltage GND, so voltage Vns is applied to capacitor Ca. When the voltage at capacitor Ca changes from Vn to Vns, a charge corresponding to the amount of voltage change is accumulated in capacitor Cb. The output voltage Vout of operational amplifier 101 is roughly represented by the following formula.Vout=(Ca/Cb)×(Vns−Vn)  (1)
As shown in formula (1), the amplifier shown in FIG. 26 amplifies the difference between dark level and signal level (Vns−Vn) at a gain according to the capacitance ratio between capacitors Ca and Cb.
When an amplifier is provided for each column of the image sensor, variation in gain due to mismatching of electrostatic capacitance will be a problem.
Precision in matching of electrostatic capacitance is limited by masking processing. Even when relatively large capacitors are formed with the processes of recent years, the precision remains at around 0.1%. This precision is equal to a resolution of 10 bits. When a dark scene is photographed and additional signal amplification is performed outside the camera system, an error of 0.1% instantly produces visible noise. The noise accompanying variation in amplifier gain appears as a line running from the top to the bottom on the screen. When using a wide dynamic range technique to adaptively change the gain in each column, the problem of this noise becomes even more serious.
The minimum size of capacitor Cb is limited by both electrostatic capacitance matching precision and thermal noise. When high gain is required with the amplifier shown in FIG. 26, the size of capacitor Ca must be large. This creates a problem of the integrated circuit surface area becoming large. Capacitor Ca is divided into multiple unit capacitors to make gain programmable and a switch circuit to switch connections between them must be provided. This causes the surface area to become even larger. Therefore, the amplifier shown in FIG. 26 is unsuitable for a system with a high degree of parallelism where amplification is performed in each column of the image sensor.
Increasing the gain in the amplifier shown in FIG. 26 decreases the amount of feedback in operational amplifier 101. This causes further deterioration in the dynamic characteristics. The drive capability drops when the amount of feedback decreases, so the problem that operational amplifier 101 becomes unable to drive later-stage circuitry occurs. When the direct current gain of operational amplifier 101 is increased to broaden the gain bandwidth to avoid such problems, the problem that power consumption and circuit surface area increase is produced. Therefore, gain that can be achieved with the amplifier shown in FIG. 26 is actually limited to 8 times to 16 times. When higher gain is required, a separate amplifying stage will be provided, so increased power consumption and circuit surface area are unavoidable.
The present invention was devised in consideration of this situation, with the objective of providing an amplifying circuit with which increased power consumption and circuit surface area can be limited, and an imaging device provided with such an amplifying circuit.